1 /// Types and constants of ARM64 architecture 2 module capstone.arm64; 3 4 import std.variant; 5 import std.exception: enforce; 6 7 import capstone.internal; 8 import capstone.utils; 9 10 /** Instruction's operand referring to memory 11 12 This is associated with the `Arm64OpType.mem` operand type 13 */ 14 struct Arm64OpMem { 15 Arm64Register base; /// Base register 16 Arm64Register index; /// Index register 17 int disp; /// displacement/offset value 18 } 19 20 /// Optional shift 21 struct Arm64Shift{ 22 Arm64ShiftType type; /// Type of shift 23 uint value; /// value (constant or register) to shift by 24 } 25 26 /// Tagged union of possible operand values 27 alias Arm64OperandValue = TaggedUnion!(Arm64Register, "reg", long, "imm", double, "fp", Arm64OpMem, "mem", Arm64PState, "pstate", uint, "sys", Arm64PrefetchOp, "prefetch", Arm64BarrierOp, "barrier"); 28 29 /// Instruction operand 30 struct Arm64Op { 31 int vectorIndex; /// Vector index for some vector operands (or -1 if irrelevant) 32 Arm64Vas vas; /// Vector arrangement specifier 33 Arm64Vess vess; /// Vector element size specifier 34 Arm64Shift shift; /// Potential shifting of operand 35 Arm64Extender ext; /// Extender type of this operand 36 Arm64OpType type; /// Operand type 37 Arm64OperandValue value; /// Operand value of type `type` 38 alias value this; /// Conventient access to value (as in original bindings) 39 40 package this(cs_arm64_op internal){ 41 vectorIndex = internal.vector_index; 42 vas = internal.vas; 43 vess = internal.vess; 44 shift = internal.shift; 45 ext = internal.ext; 46 type = internal.type; 47 48 final switch(internal.type){ 49 case Arm64OpType.invalid: 50 break; 51 case Arm64OpType.reg, Arm64OpType.reg_mrs, Arm64OpType.reg_msr: 52 value.reg = internal.reg; 53 break; 54 case Arm64OpType.imm, Arm64OpType.cimm: 55 value.imm = internal.imm; 56 break; 57 case Arm64OpType.mem: 58 value.mem = internal.mem; 59 break; 60 case Arm64OpType.fp: 61 value.fp = internal.fp; 62 break; 63 case Arm64OpType.pstate: 64 value.pstate = internal.pstate; 65 break; 66 case Arm64OpType.sys: 67 value.sys = internal.sys; 68 break; 69 case Arm64OpType.prefetch: 70 value.prefetch = internal.prefetch; 71 break; 72 case Arm64OpType.barrier: 73 value.barrier = internal.barrier; 74 break; 75 } 76 } 77 } 78 79 /// ARM64-specific information about an instruction 80 struct Arm64InstructionDetail { 81 Arm64Cc cc; /// Conditional code for this instruction 82 bool updateFlags; /// Does this instruction update flags? 83 bool writeback; /// Does this instruction request writeback? 84 85 Arm64Op[] operands; /// Operands for this instruction. 86 87 package this(cs_arch_detail arch_detail){ 88 this(arch_detail.arm64); 89 } 90 package this(cs_arm64 internal){ 91 cc = internal.cc; 92 updateFlags = internal.update_flags; 93 writeback = internal.writeback; 94 95 foreach(op; internal.operands[0..internal.op_count]) 96 operands ~= Arm64Op(op); 97 } 98 } 99 100 //============================================================================= 101 // Constants 102 //============================================================================= 103 104 /// ARM64 shift type 105 enum Arm64ShiftType { 106 invalid = 0, /// Invalid 107 lsl = 1, /// Logical shift left 108 msl = 2, /// Move shift left 109 lsr = 3, /// Logical shift right 110 asr = 4, /// Arithmetic shift right 111 ror = 5, /// Rotate right 112 } 113 114 /// ARM64 extender type 115 enum Arm64Extender { 116 invalid = 0, 117 uxtb = 1, 118 uxth = 2, 119 uxtw = 3, 120 uxtx = 4, 121 sxtb = 5, 122 sxth = 6, 123 sxtw = 7, 124 sxtx = 8, 125 } 126 127 /// ARM64 condition code 128 enum Arm64Cc { 129 invalid = 0, 130 eq = 1, /// Equal 131 ne = 2, /// Not equal: Not equal, or unordered 132 hs = 3, /// Unsigned higher or same: >, ==, or unordered 133 lo = 4, /// Unsigned lower or same: Less than 134 mi = 5, /// Minus, negative: Less than 135 pl = 6, /// Plus, positive or zero: >, ==, or unordered 136 vs = 7, /// Overflow: Unordered 137 vc = 8, /// No overflow: Ordered 138 hi = 9, /// Unsigned higher: Greater than, or unordered 139 ls = 10, /// Unsigned lower or same: Less than or equal 140 ge = 11, /// Greater than or equal: Greater than or equal 141 lt = 12, /// Less than: Less than, or unordered 142 gt = 13, /// Signed greater than: Greater than 143 le = 14, /// Signed less than or equal: <, ==, or unordered 144 al = 15, /// Always (unconditional): Always (unconditional) 145 146 nv = 16, /// Always (unconditional): Always (unconditional) - exists purely to disassemble 0b1111 147 } 148 149 /// System registers for MRS 150 enum Arm64MrsReg { 151 invalid = 0, 152 mdccsr_el0 = 0x9808, // 10 011 0000 0001 000 153 dbgdtrrx_el0 = 0x9828, // 10 011 0000 0101 000 154 mdrar_el1 = 0x8080, // 10 000 0001 0000 000 155 oslsr_el1 = 0x808c, // 10 000 0001 0001 100 156 dbgauthstatus_el1 = 0x83f6, // 10 000 0111 1110 110 157 pmceid0_el0 = 0xdce6, // 11 011 1001 1100 110 158 pmceid1_el0 = 0xdce7, // 11 011 1001 1100 111 159 midr_el1 = 0xc000, // 11 000 0000 0000 000 160 ccsidr_el1 = 0xc800, // 11 001 0000 0000 000 161 clidr_el1 = 0xc801, // 11 001 0000 0000 001 162 ctr_el0 = 0xd801, // 11 011 0000 0000 001 163 mpidr_el1 = 0xc005, // 11 000 0000 0000 101 164 revidr_el1 = 0xc006, // 11 000 0000 0000 110 165 aidr_el1 = 0xc807, // 11 001 0000 0000 111 166 dczid_el0 = 0xd807, // 11 011 0000 0000 111 167 id_pfr0_el1 = 0xc008, // 11 000 0000 0001 000 168 id_pfr1_el1 = 0xc009, // 11 000 0000 0001 001 169 id_dfr0_el1 = 0xc00a, // 11 000 0000 0001 010 170 id_afr0_el1 = 0xc00b, // 11 000 0000 0001 011 171 id_mmfr0_el1 = 0xc00c, // 11 000 0000 0001 100 172 id_mmfr1_el1 = 0xc00d, // 11 000 0000 0001 101 173 id_mmfr2_el1 = 0xc00e, // 11 000 0000 0001 110 174 id_mmfr3_el1 = 0xc00f, // 11 000 0000 0001 111 175 id_isar0_el1 = 0xc010, // 11 000 0000 0010 000 176 id_isar1_el1 = 0xc011, // 11 000 0000 0010 001 177 id_isar2_el1 = 0xc012, // 11 000 0000 0010 010 178 id_isar3_el1 = 0xc013, // 11 000 0000 0010 011 179 id_isar4_el1 = 0xc014, // 11 000 0000 0010 100 180 id_isar5_el1 = 0xc015, // 11 000 0000 0010 101 181 id_a64pfr0_el1 = 0xc020, // 11 000 0000 0100 000 182 id_a64pfr1_el1 = 0xc021, // 11 000 0000 0100 001 183 id_a64dfr0_el1 = 0xc028, // 11 000 0000 0101 000 184 id_a64dfr1_el1 = 0xc029, // 11 000 0000 0101 001 185 id_a64afr0_el1 = 0xc02c, // 11 000 0000 0101 100 186 id_a64afr1_el1 = 0xc02d, // 11 000 0000 0101 101 187 id_a64isar0_el1 = 0xc030, // 11 000 0000 0110 000 188 id_a64isar1_el1 = 0xc031, // 11 000 0000 0110 001 189 id_a64mmfr0_el1 = 0xc038, // 11 000 0000 0111 000 190 id_a64mmfr1_el1 = 0xc039, // 11 000 0000 0111 001 191 mvfr0_el1 = 0xc018, // 11 000 0000 0011 000 192 mvfr1_el1 = 0xc019, // 11 000 0000 0011 001 193 mvfr2_el1 = 0xc01a, // 11 000 0000 0011 010 194 rvbar_el1 = 0xc601, // 11 000 1100 0000 001 195 rvbar_el2 = 0xe601, // 11 100 1100 0000 001 196 rvbar_el3 = 0xf601, // 11 110 1100 0000 001 197 isr_el1 = 0xc608, // 11 000 1100 0001 000 198 cntpct_el0 = 0xdf01, // 11 011 1110 0000 001 199 cntvct_el0 = 0xdf02, // 11 011 1110 0000 010 200 201 // Trace registers 202 trcstatr = 0x8818, // 10 001 0000 0011 000 203 trcidr8 = 0x8806, // 10 001 0000 0000 110 204 trcidr9 = 0x880e, // 10 001 0000 0001 110 205 trcidr10 = 0x8816, // 10 001 0000 0010 110 206 trcidr11 = 0x881e, // 10 001 0000 0011 110 207 trcidr12 = 0x8826, // 10 001 0000 0100 110 208 trcidr13 = 0x882e, // 10 001 0000 0101 110 209 trcidr0 = 0x8847, // 10 001 0000 1000 111 210 trcidr1 = 0x884f, // 10 001 0000 1001 111 211 trcidr2 = 0x8857, // 10 001 0000 1010 111 212 trcidr3 = 0x885f, // 10 001 0000 1011 111 213 trcidr4 = 0x8867, // 10 001 0000 1100 111 214 trcidr5 = 0x886f, // 10 001 0000 1101 111 215 trcidr6 = 0x8877, // 10 001 0000 1110 111 216 trcidr7 = 0x887f, // 10 001 0000 1111 111 217 trcoslsr = 0x888c, // 10 001 0001 0001 100 218 trcpdsr = 0x88ac, // 10 001 0001 0101 100 219 trcdevaff0 = 0x8bd6, // 10 001 0111 1010 110 220 trcdevaff1 = 0x8bde, // 10 001 0111 1011 110 221 trclsr = 0x8bee, // 10 001 0111 1101 110 222 trcauthstatus = 0x8bf6, // 10 001 0111 1110 110 223 trcdevarch = 0x8bfe, // 10 001 0111 1111 110 224 trcdevid = 0x8b97, // 10 001 0111 0010 111 225 trcdevtype = 0x8b9f, // 10 001 0111 0011 111 226 trcpidr4 = 0x8ba7, // 10 001 0111 0100 111 227 trcpidr5 = 0x8baf, // 10 001 0111 0101 111 228 trcpidr6 = 0x8bb7, // 10 001 0111 0110 111 229 trcpidr7 = 0x8bbf, // 10 001 0111 0111 111 230 trcpidr0 = 0x8bc7, // 10 001 0111 1000 111 231 trcpidr1 = 0x8bcf, // 10 001 0111 1001 111 232 trcpidr2 = 0x8bd7, // 10 001 0111 1010 111 233 trcpidr3 = 0x8bdf, // 10 001 0111 1011 111 234 trccidr0 = 0x8be7, // 10 001 0111 1100 111 235 trccidr1 = 0x8bef, // 10 001 0111 1101 111 236 trccidr2 = 0x8bf7, // 10 001 0111 1110 111 237 trccidr3 = 0x8bff, // 10 001 0111 1111 111 238 239 // GICv3 registers 240 icc_iar1_el1 = 0xc660, // 11 000 1100 1100 000 241 icc_iar0_el1 = 0xc640, // 11 000 1100 1000 000 242 icc_hppir1_el1 = 0xc662, // 11 000 1100 1100 010 243 icc_hppir0_el1 = 0xc642, // 11 000 1100 1000 010 244 icc_rpr_el1 = 0xc65b, // 11 000 1100 1011 011 245 ich_vtr_el2 = 0xe659, // 11 100 1100 1011 001 246 ich_eisr_el2 = 0xe65b, // 11 100 1100 1011 011 247 ich_elsr_el2 = 0xe65d, // 11 100 1100 1011 101 248 } 249 250 /// System registers for MSR 251 enum Arm64MsrReg { 252 dbgdtrtx_el0 = 0x9828, // 10 011 0000 0101 000 253 oslar_el1 = 0x8084, // 10 000 0001 0000 100 254 pmswinc_el0 = 0xdce4, // 11 011 1001 1100 100 255 256 // Trace registers 257 trcoslar = 0x8884, // 10 001 0001 0000 100 258 trclar = 0x8be6, // 10 001 0111 1100 110 259 260 // GICv3 registers 261 icc_eoir1_el1 = 0xc661, // 11 000 1100 1100 001 262 icc_eoir0_el1 = 0xc641, // 11 000 1100 1000 001 263 icc_dir_el1 = 0xc659, // 11 000 1100 1011 001 264 icc_sgi1r_el1 = 0xc65d, // 11 000 1100 1011 101 265 icc_asgi1r_el1 = 0xc65e, // 11 000 1100 1011 110 266 icc_sgi0r_el1 = 0xc65f, // 11 000 1100 1011 111 267 } 268 269 /// System PState Field (MSR instruction) 270 enum Arm64PState { 271 invalid = 0, 272 spsel = 0x05, 273 daifset = 0x1e, 274 daifclr = 0x1f 275 } 276 277 /// Vector arrangement specifier (for FloatingPoint/Advanced SIMD instructions) 278 enum Arm64Vas { 279 invalid = 0, 280 vas_8b, 281 vas_16b, 282 vas_4h, 283 vas_8h, 284 vas_2s, 285 vas_4s, 286 vas_1d, 287 vas_2d, 288 vas_1q, 289 } 290 291 /// Vector element size specifier 292 enum Arm64Vess { 293 invalid = 0, 294 b, 295 h, 296 s, 297 d, 298 } 299 300 /// Memory barrier operands 301 enum Arm64BarrierOp { 302 invalid = 0, 303 oshld = 0x1, 304 oshst = 0x2, 305 osh = 0x3, 306 nshld = 0x5, 307 nshst = 0x6, 308 nsh = 0x7, 309 ishld = 0x9, 310 ishst = 0xa, 311 ish = 0xb, 312 ld = 0xd, 313 st = 0xe, 314 sy = 0xf 315 } 316 317 /// Operand type for instruction's operands 318 enum Arm64OpType { 319 invalid = 0, /// Invalid 320 reg, /// Register operand (`Arm64Register`) 321 imm, /// Immediate operand (`long`) 322 mem, /// Memory operand (`Arm64OpMem`) 323 fp, /// Floating-point operand (`double`) 324 cimm = 64, /// C-Immediate (`long`) 325 reg_mrs, /// MRS register operand (`Arm64Register`) 326 reg_msr, /// MSR register operand (`Arm64Register`) 327 pstate, /// P-state operand (`Arm64PState`) 328 sys, /// Sys operand for ic/dc/at/tlbi instructions (`uint`) 329 prefetch, /// Prefetch operand prfm (`Arm64PrefetchOp`) 330 barrier, /// Memory barrier operand for isb/dmb/dsb instructions (`Arm64BarrierOp`) 331 } 332 333 /// TLBI operations 334 enum Arm64TlbiOp { 335 invalid = 0, 336 vmalle1is, 337 vae1is, 338 aside1is, 339 vaae1is, 340 vale1is, 341 vaale1is, 342 alle2is, 343 vae2is, 344 alle1is, 345 vale2is, 346 vmalls12e1is, 347 alle3is, 348 vae3is, 349 vale3is, 350 ipas2e1is, 351 ipas2le1is, 352 ipas2e1, 353 ipas2le1, 354 vmalle1, 355 vae1, 356 aside1, 357 vaae1, 358 vale1, 359 vaale1, 360 alle2, 361 vae2, 362 alle1, 363 vale2, 364 vmalls12e1, 365 alle3, 366 vae3, 367 vale3, 368 } 369 370 /// AT operations 371 enum Arm64AtOp { 372 s1e1r, 373 s1e1w, 374 s1e0r, 375 s1e0w, 376 s1e2r, 377 s1e2w, 378 s12e1r, 379 s12e1w, 380 s12e0r, 381 s12e0w, 382 s1e3r, 383 s1e3w, 384 } 385 386 /// DC operations 387 enum Arm64DcOp { 388 invalid = 0, 389 zva, 390 ivac, 391 isw, 392 cvac, 393 csw, 394 cvau, 395 civac, 396 cisw, 397 } 398 399 /// IC operations 400 enum Arm64IcOp { 401 invalid = 0, 402 ialluis, 403 iallu, 404 ivau, 405 } 406 407 /// Prefetch operations (PRFM) 408 enum Arm64PrefetchOp { 409 invalid = 0, 410 pldl1keep = 0x00 + 1, 411 pldl1strm = 0x01 + 1, 412 pldl2keep = 0x02 + 1, 413 pldl2strm = 0x03 + 1, 414 pldl3keep = 0x04 + 1, 415 pldl3strm = 0x05 + 1, 416 plil1keep = 0x08 + 1, 417 plil1strm = 0x09 + 1, 418 plil2keep = 0x0a + 1, 419 plil2strm = 0x0b + 1, 420 plil3keep = 0x0c + 1, 421 plil3strm = 0x0d + 1, 422 pstl1keep = 0x10 + 1, 423 pstl1strm = 0x11 + 1, 424 pstl2keep = 0x12 + 1, 425 pstl2strm = 0x13 + 1, 426 pstl3keep = 0x14 + 1, 427 pstl3strm = 0x15 + 1, 428 } 429 430 /// ARM64 registers 431 enum Arm64Register { 432 invalid = 0, 433 434 x29, 435 x30, 436 nzcv, 437 sp, 438 wsp, 439 wzr, 440 xzr, 441 b0, 442 b1, 443 b2, 444 b3, 445 b4, 446 b5, 447 b6, 448 b7, 449 b8, 450 b9, 451 b10, 452 b11, 453 b12, 454 b13, 455 b14, 456 b15, 457 b16, 458 b17, 459 b18, 460 b19, 461 b20, 462 b21, 463 b22, 464 b23, 465 b24, 466 b25, 467 b26, 468 b27, 469 b28, 470 b29, 471 b30, 472 b31, 473 d0, 474 d1, 475 d2, 476 d3, 477 d4, 478 d5, 479 d6, 480 d7, 481 d8, 482 d9, 483 d10, 484 d11, 485 d12, 486 d13, 487 d14, 488 d15, 489 d16, 490 d17, 491 d18, 492 d19, 493 d20, 494 d21, 495 d22, 496 d23, 497 d24, 498 d25, 499 d26, 500 d27, 501 d28, 502 d29, 503 d30, 504 d31, 505 h0, 506 h1, 507 h2, 508 h3, 509 h4, 510 h5, 511 h6, 512 h7, 513 h8, 514 h9, 515 h10, 516 h11, 517 h12, 518 h13, 519 h14, 520 h15, 521 h16, 522 h17, 523 h18, 524 h19, 525 h20, 526 h21, 527 h22, 528 h23, 529 h24, 530 h25, 531 h26, 532 h27, 533 h28, 534 h29, 535 h30, 536 h31, 537 q0, 538 q1, 539 q2, 540 q3, 541 q4, 542 q5, 543 q6, 544 q7, 545 q8, 546 q9, 547 q10, 548 q11, 549 q12, 550 q13, 551 q14, 552 q15, 553 q16, 554 q17, 555 q18, 556 q19, 557 q20, 558 q21, 559 q22, 560 q23, 561 q24, 562 q25, 563 q26, 564 q27, 565 q28, 566 q29, 567 q30, 568 q31, 569 s0, 570 s1, 571 s2, 572 s3, 573 s4, 574 s5, 575 s6, 576 s7, 577 s8, 578 s9, 579 s10, 580 s11, 581 s12, 582 s13, 583 s14, 584 s15, 585 s16, 586 s17, 587 s18, 588 s19, 589 s20, 590 s21, 591 s22, 592 s23, 593 s24, 594 s25, 595 s26, 596 s27, 597 s28, 598 s29, 599 s30, 600 s31, 601 w0, 602 w1, 603 w2, 604 w3, 605 w4, 606 w5, 607 w6, 608 w7, 609 w8, 610 w9, 611 w10, 612 w11, 613 w12, 614 w13, 615 w14, 616 w15, 617 w16, 618 w17, 619 w18, 620 w19, 621 w20, 622 w21, 623 w22, 624 w23, 625 w24, 626 w25, 627 w26, 628 w27, 629 w28, 630 w29, 631 w30, 632 x0, 633 x1, 634 x2, 635 x3, 636 x4, 637 x5, 638 x6, 639 x7, 640 x8, 641 x9, 642 x10, 643 x11, 644 x12, 645 x13, 646 x14, 647 x15, 648 x16, 649 x17, 650 x18, 651 x19, 652 x20, 653 x21, 654 x22, 655 x23, 656 x24, 657 x25, 658 x26, 659 x27, 660 x28, 661 662 v0, 663 v1, 664 v2, 665 v3, 666 v4, 667 v5, 668 v6, 669 v7, 670 v8, 671 v9, 672 v10, 673 v11, 674 v12, 675 v13, 676 v14, 677 v15, 678 v16, 679 v17, 680 v18, 681 v19, 682 v20, 683 v21, 684 v22, 685 v23, 686 v24, 687 v25, 688 v26, 689 v27, 690 v28, 691 v29, 692 v30, 693 v31, 694 695 // Alias registers 696 ip1 = x16, 697 ip0 = x17, 698 fp = x29, 699 lr = x30, 700 } 701 702 /// ARM64 instruction 703 enum Arm64InstructionId { 704 invalid = 0, 705 706 abs, 707 adc, 708 addhn, 709 addhn2, 710 addp, 711 add, 712 addv, 713 adr, 714 adrp, 715 aesd, 716 aese, 717 aesimc, 718 aesmc, 719 and, 720 asr, 721 b, 722 bfm, 723 bic, 724 bif, 725 bit, 726 bl, 727 blr, 728 br, 729 brk, 730 bsl, 731 cbnz, 732 cbz, 733 ccmn, 734 ccmp, 735 clrex, 736 cls, 737 clz, 738 cmeq, 739 cmge, 740 cmgt, 741 cmhi, 742 cmhs, 743 cmle, 744 cmlt, 745 cmtst, 746 cnt, 747 mov, 748 crc32b, 749 crc32cb, 750 crc32ch, 751 crc32cw, 752 crc32cx, 753 crc32h, 754 crc32w, 755 crc32x, 756 csel, 757 csinc, 758 csinv, 759 csneg, 760 dcps1, 761 dcps2, 762 dcps3, 763 dmb, 764 drps, 765 dsb, 766 dup, 767 eon, 768 eor, 769 eret, 770 extr, 771 ext, 772 fabd, 773 fabs, 774 facge, 775 facgt, 776 fadd, 777 faddp, 778 fccmp, 779 fccmpe, 780 fcmeq, 781 fcmge, 782 fcmgt, 783 fcmle, 784 fcmlt, 785 fcmp, 786 fcmpe, 787 fcsel, 788 fcvtas, 789 fcvtau, 790 fcvt, 791 fcvtl, 792 fcvtl2, 793 fcvtms, 794 fcvtmu, 795 fcvtns, 796 fcvtnu, 797 fcvtn, 798 fcvtn2, 799 fcvtps, 800 fcvtpu, 801 fcvtxn, 802 fcvtxn2, 803 fcvtzs, 804 fcvtzu, 805 fdiv, 806 fmadd, 807 fmax, 808 fmaxnm, 809 fmaxnmp, 810 fmaxnmv, 811 fmaxp, 812 fmaxv, 813 fmin, 814 fminnm, 815 fminnmp, 816 fminnmv, 817 fminp, 818 fminv, 819 fmla, 820 fmls, 821 fmov, 822 fmsub, 823 fmul, 824 fmulx, 825 fneg, 826 fnmadd, 827 fnmsub, 828 fnmul, 829 frecpe, 830 frecps, 831 frecpx, 832 frinta, 833 frinti, 834 frintm, 835 frintn, 836 frintp, 837 frintx, 838 frintz, 839 frsqrte, 840 frsqrts, 841 fsqrt, 842 fsub, 843 hint, 844 hlt, 845 hvc, 846 ins, 847 848 isb, 849 ld1, 850 ld1r, 851 ld2r, 852 ld2, 853 ld3r, 854 ld3, 855 ld4, 856 ld4r, 857 858 ldarb, 859 ldarh, 860 ldar, 861 ldaxp, 862 ldaxrb, 863 ldaxrh, 864 ldaxr, 865 ldnp, 866 ldp, 867 ldpsw, 868 ldrb, 869 ldr, 870 ldrh, 871 ldrsb, 872 ldrsh, 873 ldrsw, 874 ldtrb, 875 ldtrh, 876 ldtrsb, 877 878 ldtrsh, 879 ldtrsw, 880 ldtr, 881 ldurb, 882 ldur, 883 ldurh, 884 ldursb, 885 ldursh, 886 ldursw, 887 ldxp, 888 ldxrb, 889 ldxrh, 890 ldxr, 891 lsl, 892 lsr, 893 madd, 894 mla, 895 mls, 896 movi, 897 movk, 898 movn, 899 movz, 900 mrs, 901 msr, 902 msub, 903 mul, 904 mvni, 905 neg, 906 not, 907 orn, 908 orr, 909 pmull2, 910 pmull, 911 pmul, 912 prfm, 913 prfum, 914 raddhn, 915 raddhn2, 916 rbit, 917 ret, 918 rev16, 919 rev32, 920 rev64, 921 rev, 922 ror, 923 rshrn2, 924 rshrn, 925 rsubhn, 926 rsubhn2, 927 sabal2, 928 sabal, 929 930 saba, 931 sabdl2, 932 sabdl, 933 sabd, 934 sadalp, 935 saddlp, 936 saddlv, 937 saddl2, 938 saddl, 939 saddw2, 940 saddw, 941 sbc, 942 sbfm, 943 scvtf, 944 sdiv, 945 sha1c, 946 sha1h, 947 sha1m, 948 sha1p, 949 sha1su0, 950 sha1su1, 951 sha256h2, 952 sha256h, 953 sha256su0, 954 sha256su1, 955 shadd, 956 shll2, 957 shll, 958 shl, 959 shrn2, 960 shrn, 961 shsub, 962 sli, 963 smaddl, 964 smaxp, 965 smaxv, 966 smax, 967 smc, 968 sminp, 969 sminv, 970 smin, 971 smlal2, 972 smlal, 973 smlsl2, 974 smlsl, 975 smov, 976 smsubl, 977 smulh, 978 smull2, 979 smull, 980 sqabs, 981 sqadd, 982 sqdmlal, 983 sqdmlal2, 984 sqdmlsl, 985 sqdmlsl2, 986 sqdmulh, 987 sqdmull, 988 sqdmull2, 989 sqneg, 990 sqrdmulh, 991 sqrshl, 992 sqrshrn, 993 sqrshrn2, 994 sqrshrun, 995 sqrshrun2, 996 sqshlu, 997 sqshl, 998 sqshrn, 999 sqshrn2, 1000 sqshrun, 1001 sqshrun2, 1002 sqsub, 1003 sqxtn2, 1004 sqxtn, 1005 sqxtun2, 1006 sqxtun, 1007 srhadd, 1008 sri, 1009 srshl, 1010 srshr, 1011 srsra, 1012 sshll2, 1013 sshll, 1014 sshl, 1015 sshr, 1016 ssra, 1017 ssubl2, 1018 ssubl, 1019 ssubw2, 1020 ssubw, 1021 st1, 1022 st2, 1023 st3, 1024 st4, 1025 stlrb, 1026 stlrh, 1027 stlr, 1028 stlxp, 1029 stlxrb, 1030 stlxrh, 1031 stlxr, 1032 stnp, 1033 stp, 1034 strb, 1035 str, 1036 strh, 1037 sttrb, 1038 sttrh, 1039 sttr, 1040 sturb, 1041 stur, 1042 sturh, 1043 stxp, 1044 stxrb, 1045 stxrh, 1046 stxr, 1047 subhn, 1048 subhn2, 1049 sub, 1050 suqadd, 1051 svc, 1052 sysl, 1053 sys, 1054 tbl, 1055 tbnz, 1056 tbx, 1057 tbz, 1058 trn1, 1059 trn2, 1060 uabal2, 1061 uabal, 1062 uaba, 1063 uabdl2, 1064 uabdl, 1065 uabd, 1066 uadalp, 1067 uaddlp, 1068 uaddlv, 1069 uaddl2, 1070 uaddl, 1071 uaddw2, 1072 uaddw, 1073 ubfm, 1074 ucvtf, 1075 udiv, 1076 uhadd, 1077 uhsub, 1078 umaddl, 1079 umaxp, 1080 umaxv, 1081 umax, 1082 uminp, 1083 uminv, 1084 umin, 1085 umlal2, 1086 umlal, 1087 umlsl2, 1088 umlsl, 1089 umov, 1090 umsubl, 1091 umulh, 1092 umull2, 1093 umull, 1094 uqadd, 1095 uqrshl, 1096 uqrshrn, 1097 uqrshrn2, 1098 uqshl, 1099 uqshrn, 1100 uqshrn2, 1101 uqsub, 1102 uqxtn2, 1103 uqxtn, 1104 urecpe, 1105 urhadd, 1106 urshl, 1107 urshr, 1108 ursqrte, 1109 ursra, 1110 ushll2, 1111 ushll, 1112 ushl, 1113 ushr, 1114 usqadd, 1115 usra, 1116 usubl2, 1117 usubl, 1118 usubw2, 1119 usubw, 1120 uzp1, 1121 uzp2, 1122 xtn2, 1123 xtn, 1124 zip1, 1125 zip2, 1126 1127 // Alias instructions 1128 mneg, 1129 umnegl, 1130 smnegl, 1131 nop, 1132 yield, 1133 wfe, 1134 wfi, 1135 sev, 1136 sevl, 1137 ngc, 1138 sbfiz, 1139 ubfiz, 1140 sbfx, 1141 ubfx, 1142 bfi, 1143 bfxil, 1144 cmn, 1145 mvn, 1146 tst, 1147 cset, 1148 cinc, 1149 csetm, 1150 cinv, 1151 cneg, 1152 sxtb, 1153 sxth, 1154 sxtw, 1155 cmp, 1156 uxtb, 1157 uxth, 1158 uxtw, 1159 ic, 1160 dc, 1161 at, 1162 tlbi 1163 } 1164 1165 /// Group of ARM64 instructions 1166 enum Arm64InstructionGroup { 1167 invalid = 0, 1168 1169 // Generic groups 1170 // All jump instructions (conditional+direct+indirect jumps) 1171 jump, 1172 1173 // Architecture-specific groups 1174 crypto = 128, 1175 fparmv8, 1176 neon, 1177 crc 1178 }