Architecture-specific Detail variant
Architecture-specific instruction variant
Architecture-specific InstructionGroup variant
Architecture-specific Register variant
Architecture-specific Capstone variant
ARM condition code
Flags operand of CPS instruction
Mode operand of CPS instruction
Group of ARM instructions
ARM instruction
The memory barrier constants map directly to the 4-bit encoding of the option field for Memory Barrier operations
Operand type for instruction's operands
ARM registers
Operand type for SETEND instruction
ARM shift type
System registers for MSR
Data type for elements of vector instructions.
ARM-specific information about an instruction
Instruction's operand
Instruction's operand referring to memory
Optional shift
Union of possible operand values
Union of possible shift values